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Lower Power 3.3V CMOS Fast SRAM 256K (32K x 8-Bit)
Features
Ideal for high-performance processor secondary cache Commercial (0C to +70C) and Industrial (-40C to +85C) temperature range options Fast access times: - Commercial and Industrial: 10/12/15/20ns Low standby current (maximum): - 2mA full standby Small packages for space-efficient layouts: - 28-pin 300 mil SOJ - 28-pin TSOP Type I Produced with advanced high-performance CMOS technology Inputs and outputs are LVTTL-compatible Single 3.3V(0.3V) power supply
IDT71V256SA
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Description
The IDT71V256SA is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. The IDT71V256SA has outstanding low power characteristics while at the same time maintaining very high performance. Address access times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V desktop designs. When power management logic puts the IDT71V256SA in standby mode, its very low power characteristics contribute to extended battery life. By taking CS HIGH, the SRAM will automatically go to a low power standby mode and will remain in standby as long as CS remains HIGH. Furthermore, under full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to always be less than 6.6mW and typically will be much smaller. The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin 300 mil TSOP Type I.
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Functional Block Diagram
A0 ADDRESS DECODER A14 262,144 BIT MEMORY ARRAY
VCC GND
I/O0 INPUT DATA CIRCUIT I/O7
I/O CONTROL
CS OE WE
,
CONTROL CIRCUIT
3101 drw 01
JUNE 2002
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(c)2000 Integrated Device Technology, Inc. DSC-3101/07
IDT71V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23
Truth Table(1)
WE
VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3
3101 drw 02
CS H VHC L L L
OE X X H L X
I/O High-Z High-Z High-Z DOUT DIN
Function Standby (ISB) Standby (ISB1) Output Disable Read Write
3101 tbl 02
X X H H L
SO28-5
22 21 20 19 18 17 16 15
NOTE: 1. H = VIH, L = VIL, X = Don't Care
,
DIP/SOJ Top View
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
22 23 24 25 26 27 28 1 2 3 4 5 6 7
Absolute Maximum Ratings(1)
Symbol VCC Rating Supply Voltage Relative to GND Terminal Voltage Relative to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. -0.5 to +4.6 -0.5 to VCC+0.5 -55 to +125 -55 to +125 1.0 50 Unit V V
o
21 20 19 18 17 16 15 14 13 12 11 10 9 8
SO28-8
A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
VTERM(2) TBIAS TSTG PT
C C
o
W mA
3101 tbl 03
,
IOUT
TSOP Top View Pin Descriptions
Name A0 - A14 I/O0 - I/O7 CS WE OE GND VCC
3101 drw 03
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Input, Output, and I/O terminals; 4.6V maximum.
Description Addresses Data Input/Output Chip Select Write Enable Output Enable Ground Power
3101 tbl 01
Capacitance
Symbol CIN COUT
(TA = +25C, f = 1.0MHz, SOJ package)
Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
3101 tbl 04
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V 0.3V 3.3V 0.3V
3101 tbl 05
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IDT71V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Recommended DC Operating Conditions
Symbol VCC GND VIH VIH VIL Parameter Supply Voltage Ground Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage Min. 3.0 0 2.0 2.0 -0.3
(1)
Typ. 3.3 0
____ ____ ____
Max. 3.6 0 5.0 VCC +0.3 0.8
Unit V V V V V
3101 tbl 06
NOTE: 1. VIL (min.) = -2.0V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics(1)
Symbol ICC ISB ISB1 Parameter Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS = VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., Outputs Open, f = 0(2), VIN < VLC or VIN > VHC
(VCC = 3.3V 0.3V, VLC = 0.2V, VHC = VCC - 0.2V, Commercial and Industrial Temperture Ranges)
71V256SA10 100 20 2 71V256SA12 90 20 2 71V256SA15 85 20 2 71V256SA20 85 20 2 Unit mA mA mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC, only address inputs cycling at fMAX; f = 0 means that no inputs are cycling.
3101 tbl 07
DC Electrical Characteristics
(VCC = 3.3V 0.3V)
Symbol |ILI| |ILO| VOL VOH IDT71V256SA Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
___ ___ ___
Typ.
___ ___ ___ ___
Max. 2 2 0.4
___
Unit A A V V
3101 tbl 08
2.4
6.42 3
IDT71V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
3101 tbl 09
3.3V 320 DATAOUT 350 30pF* DATAOUT
3.3V 320
,
350
5pF*
,
3101 drw 05
3101 drw 04
Figure 1. AC Test Load *Includes scope and jig capacitances
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
AC Electrical Characteristics
(VCC = 3.3V 0.3V, Commercial and Industrial Temperature Ranges)
71V256SA10 Symbol Parameter Min. Max. 71V256SA12 Min. Max. 71V256SA15 Min. Max. 71V256SA20 Min. Max. Unit
Read Cycle
tRC tAA tACS tCLZ(1) tCHZ(1) tOE tOLZ
(1)
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Select to Output in High-Z Outp ut Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change
10
____
____
12
____
____
15
____
____
20
____
____
ns ns ns ns ns ns ns ns ns
10 10
____
12 12
____
15 15
____
20 20
____
____
____
____
____
5 0
____
5 0
____
5 0
____
5 0
____
8 6
____
8 6
____
9 7
____
10 8
____
3 2 3
3 2 3
0 0 3
0 0 3
tOHZ(1) tOH
6
____
6
____
7
____
8
____
Write Cycle
tWC tAW tCW tAS tWP tWR tDW tDH tOW
(1)
Write Cycle Time Address Valid to End-of-Write Chip Select to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from Write Time Output Active from End-of-Write Write Enable to Output in High-Z
10 9 9 0 9 0 6 0 4 1
____ ____
12 9 9 0 9 0 6 0 4 1
____ ____
15 10 10 0 10 0 7 0 4 1
____ ____
20 15 15 0 15 0 8 0 4 1
____ ____
ns ns ns ns ns ns ns ns ns ns
3101 tbl 10
____ ____ ____
____ ____ ____
____ ____ ____
____ ____ ____
____ ____ ____
____ ____ ____
____ ____ ____
____ ____ ____
____
____
____
____
tWHZ(1)
8
8
9
10
NOTE: 1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
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IDT71V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE t OLZ CS tACS t CLZ DATAOUT
(2) (2)
tOH
t OHZ
(2)
t CHZ DATA VALID
(2)
3101 drw 06
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NOTES: 1. WE is HIGH for Read cycle. 2. Transition is measured 200mV from steady state.
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID
3101 drw 07
tOH
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Timing Waveform of Read Cycle No. 3(1,3,4)
CS tACS tCLZ DATAOUT
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
(5)
t CHZ DATA VALID
(5)
3101 drw 08
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6.42 5
IDT71V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6)
t WC ADDRESS tOHZ OE t AW CS t AS WE tWHZ (5) DATAOUT
(3) (5)
tWP (6)
t WR
tOW (5)
(3)
t DW DATAIN
tDH
DATA VALID
3101 drw 09
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NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified tWP.
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,4)
t WC ADDRESS t AW CS tAS WE t DW DATAIN DATA VALID
3101 drw 10
tCW
(5)
tWR t
t DH
,
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified tWP.
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IDT71V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information Commercial and Industrial
IDT 71V256 Device Type SA Power XX Speed X Package X X Process/ Tape & Reel Temperature Range 8 Blank I Y PZ Commercial (0C to +70C) Industrial (-40C to +85C) 300 mil SOJ (SO28-5) TSOP Type I (SO28-8)
Speed in nanoseconds
* Available in SOJ package only.
3101 drw 11
6.42 7
IDT71V256SA 3.3V CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
1/7/00 Pg. 1, 3, 4, 7 Pg. 1, 2, 7 Pg. 6 Pg. 7 Pg. 8 08/09/00 02/01/01 06/21/02 Updated to new format Expanded Industrial Temperature offerings Removed 28-pin 300 mil plastic DIP package offering Removed Note No. 1 from Write Cycle No. 1 diagram; renumbered notes and footnotes Revised Ordering Information Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" Added tape and reel option to the ordering information
Pg. 7
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for Tech Support: sramhelp@idt.com 800 544-7726, x4033
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